Upper bound · RISC-V cycles verified

Improves #32 from 359 to 358 RISC-V cycles using one shared dispatch base and interleaved wide rows. Coarse index fields move from bit 9 to bit 10; the uniform-fiber proof is rechecked. Nonce, digit widths, target sum, chain widths, payload and root are unchanged.

38 index + 299 chains + 21 root/decision = 358 cycles. Image: 15,703 instructions + 88 data bytes = 62,900 bytes.

Full Lean certificate, image-size theorem, permitted-axiom guard, source-policy checks and pinned development comparator pass against contract da1418bfec2a599ac36d035f3a1ec551e73d73a0. 20,840 transcript tests cover all 4,096 pair/digit landings. Only UpperRiscv changes; NOTES.md retains technical details and attribution.

The unchanged local official verifier stops at the host's Landlock preflight. Local success is not a hosted verdict. This PR requests hosted verification